1. Field of the Invention
The invention is directed to an arrangement for a clock supply of high bit rate switching network structures in a digital narrowband switching system such as EWSD with a PLL system comprising a crystal-controlled oscillator.
2. Description of the Related Art
The previously mentioned switching networks work with a transmission speed of (128xc3x9764 kB/s)=8.192 MB/s (colloquially, xe2x80x9c8 MB/sxe2x80x9d). In such switching networks, the required synchronizing clock is achieved proceeding from a centrally generated 8 MHz system clock, namely with rigid synchronism. The necessary frame positions are also defined and forced in the various switching stages by a frame clock FMB2 that is generated phase-locked relative to the 8 MHz system clock. Due to the adequate phase reserves at the data interfaces, a synchronization on site is not required. Jitter problems are not critical; on the contrary, the jitter demands made of the generated system parts lie in the easily doable range. Traditionally, a PLL system employing a commercially obtainable crystal-controlled oscillator is used. The PLL system is provided in order to assure the phase-locked linking of the switching network clock to the clock that is generated by the central clock generator, the crystal-controlled oscillator, and converted. The required 8 MHz system clock, CLK8, and the 2 KHz frame marking or the 2 KHz frame clock, FMB2, are offered on symmetrical lines in the narrowband switching system at the traditional TTL level. The stable crystal-controlled oscillator of the PLL system achieves high-quality phase and frequency stability.
High bit rate switching network structures, however, must work with significantly higher serving speeds. It is desirable to have a serving speed of (2304xc3x9780 kB/s)=184.320 MB/s (xe2x80x9c184 MB/sxe2x80x9d), which could use correspondingly dimensioned crystal-controlled oscillators. Crystals that oscillate with the required frequencies, however, are extremely expensive, by which only the harmonics can be employed. Moreover, a central circuit-synchronous clock can no longer be employed for distribution-oriented reasons. The necessity of having to adhere to an extremely narrow frequency follow-up range is also disadvantageous.
It must be taken into consideration that clock signal edges having a spacing of 0.7 ns must be selected, by which a high-frequency phase stability of 300-400 ps (peak-to-peak) must be achieved to reliably function and to consider unavoidable jitter accumulation at the various transitions.
Thus, an object of the present invention is to specify an arrangement for a clock supply of high bit rate switching network structures with which high phase and frequency stability can also be assured in the high-frequency range.
This object is achieved by an arrangement for a clock supply of high bit-rate switching network structures in a digital narrowband switching system, comprising: a PLL system comprising a crystal-controlled oscillator that locks the switching network clock to a clock phase generated by a central clock generator and outputs a low-voltage normal bit-rate, low frequency, clock signal and a low-voltage frame clock signal for normal bit-rate switching network structures; an analog, discrete sine oscillator in a phase-locked loop that converts the normal bit-rate clock signal into a high-frequency clock signal; and a low-voltage pseudo-ECL arrangement, that, after stabilization with a reference clock, generates a high bit-rate, high frequency, clock signal suitable for high bit-rate switching network structures by division and outputs it, the low-voltage pseudo-ECL arrangement also outputting an output-side high bit-rate, high frequency, frame clock signal of the same frequency decoupled in phase position from an input-side frame clock signal that has a predetermined phase relation relative to the high bit-rate output-side clock signal. The arrangement may further comprise a feedback path via which a clock signal, that is a feedback signal, that has been stepped-down in frequency as well as converted in level can be fed back to an input-side phase detector contained within a low-voltage CMOS arrangement that also receives the input-side normal bit-rate clock signal. The arrangement may also comprise an ultra-fast comparator with a high analog gain, the ultra-fast comparator comprising a following, integrated frequency divider with two differing division rates for an output of the high bit-rate output-side clock signal and of the feedback signal. The comparator may have a high steepness for a sine signal in a zero-axis crossing at a steepness of approximately 1V/ns. This arrangement may further comprise a level converter in the feedback path, the level converter consisting of passive components and serving for a conversion of low-voltage pseudo-ECL level onto low-voltage CMOS level. The phase detector may comprise an exclusive-OR element; and a step-down device in the low-voltage CMOS structure may be provided in the form of an electrically programmable gate array that further-converts the feedback and level-converted signal into a signal having a pulse-duty factor 1:1 that is supplied to the exclusive-OR element.
The arrangement may further comprise a two-stage, passive low-pass filter preceding the analog sine oscillator and having a xe2x88x923 dB limit frequency of at least 2 times the corner frequency of a pure proportion control element part of a control loop of the arrangement without a low-pass filter. It also may comprise a clock distributor arrangement in the low-voltage pseudo-ECL arrangement that receives the high bit-rate clock signal and the high bit-rate frame clock signal coupled to it in phase position at its input side and divides these in pairs onto numerous output pairs. The arrangement may further comprise low-voltage pseudo-ECL components with low skew that are selected such that a required system jitter that is reached in the low-voltage pseudo-ECL arrangement, the low-voltage CMOS arrangement, and the clock distributor arrangement lies on the order of magnitude of xc2x1200 ps. The arrangement may further comprise a low-voltage ASIC in a low-voltage CMOS arrangement, the ASIC having integrated into it: a gate array arrangement; an analog PLL; and a comparator that is supplied by the high bit-rate clock signal and the high bit-rate frame clock signal coupled to it in phase position, the comparator having difference outputs that supply the analog PLL for converting an input-side clock frequency to double that and for, in turn, its distribution of this clock frequency with the gate array arrangement. In the arrangement, the low-frequency clock signal frequency may be approximately 2048 KHz; the output side high-frequency clock frequency may be approximately 92.162 MHz; and the high frequency frame clock signal frequency may be approximately 8 KHz.
The invention is based on the idea that the noise influence as well as the creation and accumulation of jitter in the overall clock path can be kept low with a suitable selection and dimensioning of component parts. This, on the one hand, is based on the use of low-voltage technology (in the area of 3.3 V) in the high-frequency level, particularly a low-voltage CMOS technology and a low-voltage pseudo-ECL technology. Critical sources of noise influences or sources for the creation of jitter can thus be eliminated to the farthest-reaching extent. Critical noise sources in the high-frequency range are the supply voltage, the signal level employed, the edge steepness, the entire signal spectrum, and high-impedance components.